Insulated gate bipolar semiconductor device transistor with a ladder shaped emitter

ABSTRACT

A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.

TECHNICAL FIELD

This invention relates to a semiconductor device having an insulatedgate. More particularly, the invention relates to a gate-insulatedbipolar transistor that is favorably used as a power switching element.

BACKGROUND OF THE INVENTION

As a power switching element, in recent years, there has been widelyused an element called Insulated Gate Bipolar Transistor (hereinafterreferred to as IGBT). FIGS. 10 to 13 are diagrams illustrating the basicconstitution of a conventional IGBT, wherein FIG. 10 is a plan view ofthe main surface of a semiconductor substrate illustrating theconstitution of the conventional IGBT, FIG. 11 is a sectional view ofthe IGBT along a line XI—XI of FIG. 10, FIG. 12 is a sectional view ofthe IGBT along a line XII—XII of FIG. 10, and FIG. 13 is a sectionalview of the IGBT along a line XIII—XIII of FIG. 10.

In FIGS. 10 to 13, reference numeral 50 denotes an n-layer serving as asemiconductor substrate of a first conductivity type, 51 denotes ap-collector layer serving as a collector region of a second conductivitytype, 52 denotes a collector electrode which is in contact with thep-collector layer 51, reference numeral 53 denotes a p-base layerselectively formed in the main surface of the semiconductor substrate 50and serving as a first base region of the second conductivity type, and54 denotes an n⁺-emitter layer of the first conductivity typeselectively formed in the p-base region 53. Reference numeral 55 denotesa gate electrode, and 56 denotes a gate oxide film serving as a gateinsulating film. A belt-like gate electrode 55 is formed on the surfaceof the p-base layer 53 sandwiched between the n⁻-layer 50 and then⁺-layer 54, and on the surface of the n⁻-layer 50 via the gate oxidefilm 56. Reference numeral 57 denotes a belt-like emitter electrodewhich is formed so as to be in contact with both a cleat 58 a of theladder-like n⁺-layer 54 and the p-base layer 53 exposed in the openingportion 59 of the ladder, and so as to cover them. Reference numeral 60denotes a channel region formed near the surface of the p-base layer 53sandwiched between the n⁻-layer 50 and the n⁺-layer 54.

When observed from the surface as described above, the n⁺-emitter layer54 is formed like a ladder, and a portion that comes in contact withboth the emitter of the emitter electrode 57 and the p-base layer 53, isarranged perpendicularly to the cleat 58 a of ladder and in parallelwith a crossbeam 58 b of ladder. At the end portion of a cell of astriped shape, a contact region 61 of the emitter electrode isprotruding longer than the crossbeam 58 b of ladder of the source.

Operation of the IGBT shown in FIGS. 10 to 13 will now be describedbelow. If the emitter electrode 57 is grounded, and a positive voltageis applied to the gate electrode 55 and to the collector electrode 52,then, the electric potential of the surface of the p-base layer 53 justunder the gate insulating film 56 is inverted to form an n-type channel.Electrons flow into the channel region 60 to turn the IGBT on.

In this case, the resistance decreases in the region of the n⁻-layer 50with the result that the electric conductivity of the n⁻-layer 50 ismodulated by the injection of holes into the n⁻-layer 50 from thep-collector layer 51 on the side of the collector electrode 52. Due tothe modulation in the electric conductivity, the IGBT exhibits a lowon-resistance in its ON state accompanied. On the contrary, the IGBT hasa fault that it easily latches up due to its parasitic thyristorstructure.

When the IGBT is in the ON state, holes are injected into the n⁻-layer50 from the p-collector layer 51 on the side of the collector electrode52 as described above. The holes partly extinguish upon being recombinedwith electrons injected into the n⁻-layer 50 from the n⁺-emitter layer54 through the channel, and partly escape into the emitter electrode 57passing through a pinch resistor portion in the p base layer 53.Generally, the holes are not injected into the n⁺-emitter layer 54 dueto a built-in voltage across the p-base layer 53 and the n⁺-emitterlayer 54. Accordingly, the parasitic thyristor is not turned on, and theIGBT is not latched up.

If a pinch resistance of a portion of the p-base layer 53 where the holecurrent flows through is denoted by Rb and the hole current by Jh, then,a voltage expressed by the product of Rb and Jh is produced across the pbase layer 53 and the n⁺-emitter layer 54. If this voltage becomeslarger than the above built-in voltage, the holes are injected from thep-base layer 53 to the n⁺-emitter layer 54 and, hence, electrons areinjected from the n⁺-emitter layer 54 to the p-base layer 53. That is, aparasitic npnp thyristor formed by n⁺-emitter layer 54, p-base layer 53,n⁻-layer 50 and collector layer 52, is latched up making it difficult tocontrol the current, and resulting in a breakage. The breakage can beeffectively prevented by lowering the pinch resistance Rb or the holecurrent Jh.

The IGBT chip has a structure in which the basic cells of the structureshown in FIGS. 10 to 13 are arranged like a stripe. In a portion wherethe electric current concentrates in the chip, a contrivance has beenmade so that the latch-up will not easily take place. For example, theend portion of the cell is one of the portions where the electriccurrent tends to concentrate. The emitter of this portion has a shape asshown in FIG. 10 in which the contact region 61 of the emitter electrodeprotrudes longer than the crossbeam 58 b of ladder of the source. Owingto this structure, no electron is supplied at the end portion of thecell. Therefore, only a small hole current Jh is injected from thep-collector region 51 and the parasitic thyristor is not easily turnedon.

In the conventional IGBT which is a semiconductor device having astructure which is not easily latched up, the contact region of theemitter electrode 61 is protruded longer than the crossbeam 58 b ofladder of the source at the end portion of the cell. This structure helpto improve endurance against the breakage, but at the same time itcauses the following problems.

That is, since there is formed no emitter region at the end portion ofthe cell, the channel length becomes short per a unit area, and invalidregion increases. This results in an increase in the current densityand, hence, in an increase in the ON voltage, which is a problem.

This invention was accomplished in order to solve the above problems,and has an object of providing a semiconductor device capable oflowering the ON voltage by decreasing the area of the invalid regioncompared to that of prior art yet maintaining the ability forsuppressing the latch-up to a degree comparable to that of theconventional IGBTs.

DISCLOSURE OF THE INVENTION

This invention is concerned with a semiconductor device comprising asemiconductor layer of a first conductivity type, a collector layer of asecond conductivity type formed on one surface of the semiconductorlayer, a base layer of the second conductivity type formed on the othersurface of the semiconductor layer, and an emitter layer of the firstconductivity type formed in the base layer, wherein the emitter layerhaving a shape of a ladder being constituted by two crossbeams andcleats formed between the crossbeams, and the cleat being provided evenbetween facing end portions of the two crossbeams.

This makes it possible to obtain a semiconductor structure in which thearea of the invalid region is minimized.

There are further provided an emitter electrode formed on thesemiconductor layer and having a contact part that comes in contact withthe base layer and the emitter layer, and gate electrodes formed on bothsides of the contact part on the semiconductor layer, wherein an endportion of the contact part is in contact with a first exposed portionof the base layer that is surrounded by the emitter layer.

This makes it possible to obtain a structure in which the area of theinvalid region is minimized.

Further, the emitter electrode, the gate electrodes and the collectorelectrode are maintained at predetermined potentials, respectively,thereby to form a channel region in the base layer just under the gateelectrodes formed on both sides at the end portion of the contact part.This makes it possible to obtain a structure in which the area of theinvalid region is minimized.

The end portion of the contact part is in contact with the cleat formedat the facing end portions of the two crossbeams. This makes it possibleto obtain a structure in which the area of the invalid region isminimized.

There is further provided a second exposed portion of the base layerconstituted by being surrounded by the crossbeams and the cleats,wherein a length of the first exposed portion along the crossbeams beinglarger than a length of the second exposed portion along the crossbeams.This makes it possible to prevent the semiconductor device from beinglatched up.

An impurity concentration of the emitter layer surrounding the firstexposed portion is smaller than an impurity concentration of otherportions of the emitter layer. Therefore, the emitter ballast resistanceincreases and the electronic current supplied in a state where thesemiconductor device is turned on becomes smaller than that of otherregions, making it possible to obtain a structure which prevents thelatch-up.

A width of the crossbeams surrounding the first exposed portion isnarrower than a width of the crossbeams surrounding the second exposedportion. This makes it possible to increase the emitter ballastresistance and to suppress the electronic current. It is thereforeallowed to relax the concentration of the hole current Jh and, hence, toobtain a semiconductor structure which prevents the latch-up.

A width of the cleats surrounding the first exposed portion is narrowerthan a width of other cleats of the emitter layer. This makes itpossible to increase the emitter ballast resistance and to suppress theelectronic current. It is therefore allowed to relax the concentrationof the hole current Jh and, hence, to obtain a semiconductor structurewhich prevents the latch-up.

An impurity concentration of the first exposed portion of the base layeris larger than an impurity concentration of the second exposed portionof the base layer. Accordingly, the channel portion is less likely to beformed in the base region where the impurity concentration is largerthan in other portions where the impurity concentration is not high,suppressing the flow of electronic current, relaxing the concentrationof the hole current Jh and making it possible to obtain a structurecapable of preventing the latch-up.

Further, a gate-insulating film is formed on the semiconductor layer tocover the gate electrodes, and a thickness of the gate-insulating filmon the base layer between the crossbeams surrounding the first exposedportion and the semiconductor layer, is larger than a thickness of thegate insulating film on the base layer between the crossbeamssurrounding the second exposed portion and the semiconductor layer. Thisincreases the threshold voltage at the end portion of the contact partmaking it possible to obtain a structure that prevents the latch-up.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating the constitution of a semiconductor deviceon the main surface of a semiconductor substrate according to anembodiment 1 and an embodiment 2 of this invention.

FIG. 2 is a sectional view of an IGBT along a line II—II of FIG. 1.

FIG. 3 is a sectional view of the IGBT along a line III—III of FIG. 1.

FIG. 4 is a view illustrating the constitution on the main surface ofthe semiconductor substrate of the semiconductor device according to anembodiment 3 of the invention.

FIG. 5 is a view illustrating the constitution on the main surface ofthe semiconductor substrate of the semiconductor device according to anembodiment 4 of the invention.

FIG. 6 is a view illustrating the constitution on the main surface ofthe semiconductor substrate of the semiconductor device according to anembodiment 5 of the invention.

FIG. 7 is a view illustrating the constitution on the main surface ofthe semiconductor substrate of the semiconductor device according to anembodiment 7 of the invention.

FIG. 8 is a sectional view of the semiconductor device along a lineVIII—VIII of FIG. 7.

FIG. 9 is a sectional view of the semiconductor device along a lineIX—IX of FIG. 7.

FIG. 10 is a plan view illustrating the constitution on the main surfaceof a semiconductor substrate of a conventional IGBT.

FIG. 11 is a sectional view of the IGBT along a line XI—XI of FIG. 10.

FIG. 12 is a sectional view of the IGBT along a line XII—XII of FIG. 10.

FIG. 13 is a sectional view of the IGBT along a line XIII—XIII of FIG.10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention will now be described in further detail with reference tothe accompanying drawings.

Embodiment 1

An embodiment 1 of this invention will now be described with referenceto FIGS. 1 to 3.

FIG. 1 is a view illustrating the constitution of a semiconductor deviceon the main surface of a semiconductor substrate according to theembodiment 1 of the invention. This embodiment deals with theconstitution of an IGBT that is a semiconductor device. FIG. 2 is asectional view of the IGBT along a line II—II of FIG. 1, and FIG. 3 is asectional view of the IGBT along a line III—III of FIG. 1. In thesedrawings, reference numeral 1 denotes an n⁻-layer as a semiconductorsubstrate, 2 denotes a p-collector layer as a collector region, 3denotes a collector electrode that comes into contact with thep-collector layer 2, reference numeral 4 denotes a p-base layer as abase region which is selectively formed in the main surface of then⁻-layer 1, and reference numeral 5 denotes an n⁺-emitter layerselectively formed in the p-base layer 4. Reference numeral 6 denotes agate electrode, 7 denotes a gate oxide film as a gate-insulating film,and 8 denotes an emitter electrode. The n⁺-emitter layer 5 isconstituted by two crossbeams 9 b and cleats 9 a formed therebetween inthe shape of a ladder. The cleat 9 a is formed even between the facingend portions of the two crossbeams 9 b unlike that of the prior art.Reference numeral 10 denotes an exposed portion of the p-base layer 4surrounded by the n⁺-emitter layer 5, which includes an exposed portion10 a of the p-base layer 4 surrounded by the end portion of then⁺-emitter layer 5 that comes in contact with an end portion of acontact region 12 that will be described later, and an exposed portion10 b of the p-base layer 4 surrounded by the n⁺-emitter layer 5 otherthan the end portion of the n⁺-emitter layer 5. In the embodiment 1, alength L1 of the exposed portion 10 a in a direction in parallel withthe crossbeams 9 b is equal to a length L2 of the exposed portion 10 bin a direction in parallel with the crossbeams 9 b. Reference numeral 11denotes a channel region formed in the surface of the p-base layer, and12 denotes a contact region of the emitter electrode 8 that comes incontact with the silicon surface of the p-base layer 4 or the n⁺-emitterlayer 5. The emitter electrode 8 is covering the whole surface of theIGBT. Though not diagramed, the lower side of the contact region 12 hasan end portion that is surrounded by the n⁺-emitter layer 5 like that ofthe upper side.

Next, described below is the operation of the IGBT shown in FIGS. 1 to3. In this embodiment 1, too, like in the conventional IGBT, when theemitter electrode 8 is grounded and a positive voltage is applied to thegate electrodes 6 and to the collector electrode 3, the electricpotential of near the surface of the p-base layer 4 just under thegate-insulating film 7 is inverted to form an n-type channel 11.Electrons flow through the channel region 11 to turn the IGBT on. TheIGBT chip has a constitution in which the basic cells shown in FIG. 1are arranged like a stripe. Here, however, though the p-collector layer2 is formed on the whole back surface of the chip, the basic cells arenot evenly arranged on the whole surface of the chip. In general, aguard ring is formed along the outer circumference, and the basic cellsare not formed.

When the IGBT is turned on, the holes injected into the n⁻-layer 1 fromthe p-collector layer 2, pass through from the contact region 12 to theemitter electrode 8. Here, however, the hole current from the outerperiphery of the chip tends to concentrate in the contact region 12 atthe end portion of the cell; i.e., a parasitic thyristor tends to beturned on and the latch-up breakage easily occurs.

To prevent the latch-up, it is generally using a manner to shorten thelength of the n⁺-emitter region relative to the length of the contactregion, form no MOS at the end portion of the cell, and secure a passageonly for the hole current to flow through thereby to prevent theoccurrence of latch-up.

As described above, however, this results in a decrease in the regionfor forming the channel and, hence, an increase in the ON voltage. TheON voltage stands for a voltage across the collector and the emitter ofwhen a voltage is applied to the gate of the IGBT (to turn the IGBT on)to flow a rated current across the collector and the emitter.

In this embodiment 1, the end portion of the contact region 12 issurrounded by the n⁺-emitter layer 5 if observed from the upper side asshown in FIG. 1. Due to this constitution, the region where the channelis formed becomes larger than that of the prior art and the area wherethe channel is formed increases, making it possible to decrease thecurrent density and, hence, to decrease the ON voltage compared to theprior art.

Further, since the end portion of the contact region 12 is overlapped onthe n⁺-emitter layer 5, the ON voltage can be further lowered.

The action and effect same as those described above can be exhibitedeven by a constitution in which the end portion of the contact region 12is surrounded by the n⁺-emitter layer 5 instead of being overlapped onthe n⁺-emitter layer 5.

Embodiment 2

An embodiment 2 is so constituted as to establish a relationship L1>L2between the length L1 of the exposed portion 10 a of the p-base layer 4in a direction in parallel with the crossbeams 9 b and the length L2 ofthe exposed portion 10 b of the p-base layer 4 in a direction inparallel with the crossbeams 9 b. While the IGBT is being turned on, theelectronic current is injected into the n⁻-layer 1 from the emitterelectrode 8 through the n⁺-emitter layer 5 and the channel formingregion 11. When observed from the surface, the n⁺-emitter layer 5 iscontacted to the emitter electrode 8 only at the cleats 9 a of then⁺-emitter layer 5 which is in the shape of a ladder. Therefore, theemitter ballast resistance is the smallest at the cleats 9 a andincreases as it goes away from the cleats 9 a.

Namely, the amount of supplying electrons decreases as the distanceincreases from the cleats 9 a. With the IGBT being turned on, the holessupplied from the p-collector layer 2 tend to be collected at a portionwhere there exist many electrons. Therefore, the hole density Jhdecreases in the portions of the n⁺-emitter layer 5 away from the cleatspreventing the occurrence of latch-up.

In the embodiment 2, the lengths of the crossbeams of the n⁺-emitterlayer 5 are selected to be L1>L2, whereby an MOS is formed even at theend portion of the contact region 12 of the emitter electrode 8, makingit possible to obtain a structure that prevents the latch-up whilemaintaining the area of a portion where the channel is formed. Uponsetting the relationship L1>L2 in addition to lowering the ON voltagelike in the embodiment 1, the IGBT chip becomes less subject to bebroken than that of the embodiment 1.

Embodiment 3

FIG. 4 is a diagram illustrating the constitution of the semiconductordevice on the main surface of the semiconductor substrate according toan embodiment 3 of this invention. In FIG. 4, reference numerals thesame as those of FIGS. 1 to 3 denote the same or corresponding portionsand their description is not repeated. As shown in FIG. 4, the impurityconcentration N1 of the n⁺-emitter layer 5 surrounding the end portionof the contact region 12 of the emitter electrode 8 is selected to besmaller than the impurity concentration N2 of other portions of then⁺-emitter layer 5. The n⁺-emitter layer 5 having the impurityconcentration N1 is represented by sparse dots, and the n⁺-emitter layer5 of other areas having the impurity concentration N2 is represented bydense dots. Different impurity concentrations in the n⁺-emitter layer 5are accomplished by changing the mask and by changing the number oftimes of injecting ions in the steps of fabrication.

Concerning the impurity concentration in the n⁺-emitter layer 5 in theembodiment 3, the impurity concentration in the n⁺-emitter layer 5surrounding the end portion of the contact region 12 of the emitterelectrode 8 is selected to be smaller than that of other portions,whereby the emitter ballast resistance increases, and the electroniccurrent that is supplied in a state where the IGBT is turned on becomessmaller than that of other regions, making it possible to obtain astructure that prevents the latch-up.

Embodiment 4

FIG. 5 is a diagram illustrating the constitution of the semiconductordevice on the main surface of the semiconductor substrate according toan embodiment 4 of this invention. In FIG. 5, reference numerals thesame as those of FIGS. 1 to 3 denote the same or corresponding portionsand their description is not repeated. As shown in FIG. 5, the width L4of the crossbeams 9 b in the n⁺-emitter layer 5 of a portion surroundingthe end of the contact region 12 of the emitter electrode 8, is selectedto be narrower than the width L3 of the crossbeams 9 b of other portionsof the n⁺-emitter layer 5 (L3>L4). The width of the n⁺-emitter layer 5is differed by changing the mask in the step of fabrication.

In the embodiment 4, the width L4 of the crossbeams 9 b in then⁺-emitter layer 5 of the portion surrounding the end portion of thecontact region 12 of the emitter electrode 8 is selected to be narrowerthan the width L3 of the crossbeams 9 b of the n⁺-emitter layer 5 ofother portions, whereby the emitter ballast resistance increases and theelectronic current is suppressed. Therefore, the concentration of thehole current Jh is relaxed, and can be obtained a structure preventingthe latch-up.

Embodiment 5

FIG. 6 is a diagram illustrating the constitution of the semiconductordevice on the main surface of the semiconductor substrate according toan embodiment 5 of this invention. In FIG. 6, reference numerals thesame as those of FIGS. 1 to 3 denote the same or corresponding portionsand their description is not repeated. As shown in FIG. 6, the width L6of the cleats 9 a in the n⁺-emitter layer 5 of a portion surrounding theend portion of the contact region 12 of the emitter electrode 8, isselected to be narrower than the width L5 of the cleats 9 b of otherportions of the n⁺-emitter layer 5 (L5>L6).

In the embodiment 5, the width L6 of the cleats 9 a in the n⁺-emitterlayer 5 of the portion surrounding the end portion of the contact region12 of the emitter electrode 8 is selected to be narrower than the widthL5 of the cleats 9 a of the n⁺-emitter layer 5 of other portions,whereby the emitter ballast resistance increases and the electroniccurrent is suppressed. Therefore, the concentration of the hole currentJh is relaxed, and there is obtained a structure preventing thelatch-up.

Embodiment 6

Concerning the structure described in the embodiment 1, the impurityconcentration of the p-base region 4 surrounded by the n⁺-emitter layer5 of a portion surrounding the end portion of the contact region 12 ofthe emitter electrode 8 is selected to be larger than the concentrationof the p-base region 4 of other portions.

The threshold voltage (the gate voltage necessary for forming an n-typechannel for flowing the electric current) of a portion of the p-baseregion 4 where the impurity concentration is large, is higher than thatof the portions where the impurity concentration is small. That is, evenwhen the same gate voltage is applied, the portion of the p-base region4 where the impurity concentration is large permits the channel to beformed less than other portions, and the electronic current flows less.Therefore, the concentration of the hole current Jh is relaxed, andthere is obtained a structure preventing the latch-up.

Embodiment 7

FIG. 7 is a view illustrating the constitution of the semiconductordevice on the main surface of the semiconductor substrate according toan embodiment 7 of the invention, FIG. 8 is a sectional view of the IGBTalong a line VIII—VIII of FIG. 7, and FIG. 9 is a sectional view of theIGBT along a line IX—IX of FIG. 7. In FIGS. 7 to 9, reference numeralsthe same as those of FIGS. 1 to 3 denote the same or correspondingportions, and their description is not repeated. Referring to FIG. 7,the thickness (thickness Ti indicated by an arrow in FIG. 8) of thegate-insulating film 7 formed on the surface of the p-base region 4 issmaller than the thickness (thickness T2 indicated by an arrow in FIG.9) of the gate-insulating film 7 formed on the surface of the p-baseregion 4 of a portion (sparsely dotted portion) arranged in parallelwith the contact region 12 of the emitter electrode 8 of a portion ofthe n⁺-emitter layer 5 surrounding the end portion of the contact region12 of the emitter electrode 8 and of a portion sandwiched between then⁺-emitter layer 5 indicated by the sparsely dotted portion and then⁻-layer 1. The threshold voltage of a portion where the gate insulatingfilm 7 is thickly formed becomes higher than that of the portions wherethe gate insulating film 7 is thinly formed. Upon increasing thethreshold voltage at the end portion of the contact region 12 of theemitter electrode 8, it is allowed to obtain a structure preventing thelatch-up like the structure of the embodiment 6.

As described above, this embodiment makes it possible to obtain astructure preventing the occurrence of latch-up breakage whileminimizing the area of the invalid region of the semiconductor device.

As described above, the semiconductor device of this invention is suitedfor preventing the latch-up breakage while minimizing the area of theinvalid region thereof. Accordingly, the semiconductor device of theinvention is suited as a gate bipolar transistor that can be favorablyused as a power switching element.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor layer of a first conductivity type; a collector layer of asecond conductivity type formed on one surface of said semiconductorlayer; a base layer of said second conductivity type formed on the othersurface of said semiconductor layer; an emitter layer of said firstconductivity type formed in said base layer, said emitter layer having ashape of a ladder including two crossbeams, interior cleats formedbetween said crossbeams, and exterior cleats being provided betweenfacing end portions of said two crossbeams; and an emitter electrodeformed on said semiconductor layer and having a contact part that comesin contact with said base layer and said emitter layer, said contactpart having an end portion overlapping and terminating on said exteriorcleats of the emitter layer.
 2. The semiconductor device of claim 1,further comprising: gate electrodes formed on both sides of said contactpart on said semiconductor layer; wherein said end portion of saidcontact part is in contact with a first exposed portion of said baselayer that is surrounded by said emitter layer.
 3. The semiconductordevice of claim 2, wherein said emitter electrode, said gate electrodesand said collector electrode are maintained at predetermined potentials,respectively, thereby to form a channel region in said base layer justunder said gate electrodes formed on both sides at the end portion ofsaid contact part.
 4. The semiconductor device of claims 2, furthercomprising: a second exposed portion of said base layer being surroundedby said crossbeams and said interior cleats, wherein a length of saidfirst exposed portion along said crossbeams being larger than a lengthof said second exposed portion along said crossbeams.
 5. Thesemiconductor device of claims 3, further comprising: a second exposedportion of said base layer being surrounded by said crossbeams and saidinterior cleats, wherein a length of said first exposed portion alongsaid crossbeams being larger than a length of said second exposedportion along said crossbeams.
 6. The semiconductor device of claim 2,wherein an impurity concentration of said emitter layer surrounding saidfirst exposed portion is smaller than an impurity concentration of otherportions of said emitter layer.
 7. The semiconductor device of claim 3,wherein an impurity concentration of said emitter layer surrounding saidfirst exposed portion is smaller than an impurity concentration of otherportions of said emitter layer.
 8. The semiconductor device of claim 2,wherein a width of said crossbeams surrounding said first exposedportion of said base layer is narrower than a width of said crossbeamssurrounding a second exposed portion of said base layer.
 9. Thesemiconductor device of claim 3, wherein a width of said crossbeamssurrounding said first exposed portion of said base layer is narrowerthan a width of said crossbeams surrounding a second exposed portion ofsaid base layer.
 10. The semiconductor device of claim 2, wherein awidth of cleats surrounding said first exposed portion is narrower thana width of other cleats of said emitter layer.
 11. The semiconductordevice of claim 3, wherein a width of cleats surrounding said firstexposed portion is narrower than a width of other cleats of said emitterlayer.
 12. The semiconductor device of claim 2, wherein an impurityconcentration of said first exposed portion of said base layer is largerthan an impurity concentration of a second exposed portion of said baselayer.
 13. The semiconductor device of claim 3, wherein an impurityconcentration of said first exposed portion of said base layer is largerthan an impurity concentration of a second exposed portion of said baselayer.
 14. The semiconductor device of claim 2, wherein agate-insulating film is formed on said semiconductor layer to cover saidgate electrodes, and a thickness of said gate-insulating film on saidbase layer between said crossbeams surrounding said first exposedportion and said semiconductor layer, is larger than a thickness of saidgate insulating film on said base layer between said crossbeamssurrounding a second exposed portion of said base layer and saidsemiconductor layer.
 15. The semiconductor device of claim 3, wherein agate-insulating film is formed on said semiconductor layer to cover saidgate electrodes, and a thickness of said gate-insulating film on saidbase layer between said crossbeams surrounding said first exposedportion and said semiconductor layer, is larger than a thickness of saidgate insulating film on said base layer between said crossbeamssurrounding a second exposed portion of said base layer and saidsemiconductor layer.
 16. The semiconductor device of claim 1, furthercomprising: a second exposed portion of said base layer being surroundedby said crossbeams and said interior cleats, wherein a length of saidfirst exposed portion along said crossbeams is larger than a length ofsaid second exposed portion along said crossbeams.